A memory cell formed by one transistor and one capacitor, i.e., a one-transistor, one-capacitor memory cell (e.g., dynamic random access memory (DRAM) cell and so forth) normally has the following structure. One current terminal of an access transistor is connected to a bit line, and the other current terminal is connected a storage electrode of a capacitor. Further, two memory cells are provided on one active region. For the two mutually adjacent memory cells, two gate electrodes are provided. That is, two gate electrodes are provided on one active region. Further, three source/drain regions are formed; one between the two gate electrodes and two outside the gate electrodes. The source/drain region formed between the two gate electrodes is set as a connection region to be connected to a bit line (bit line common to the two memory cells), and the bit line connection region is connected to the bit line. The source/drain regions formed outside the two gate electrodes are set as connection regions to be connected to capacitors, and the two capacitor connection regions are connected to the capacitors.
Memory cells are arranged in a matrix. The memory cells thus arranged in a matrix are normally provided with word lines in the column direction and bit lines in the row direction. As a method of arranging the memory cells, the word lines, the bit lines, and so forth, an arrangement system based on open bit lines and an arrangement system based on folded bit lines are known. In the open bit line system, two bit lines of different memory cell areas are connected to one sense amplifier. With this configuration, noise generated in one of the memory cell areas appears only in one of the paired bit lines. Therefore, the open bit line system has an advantage of being capable of reducing the area occupied by each memory cell, but has a disadvantage of being susceptible to noise. Meanwhile, in the folded bit line system, two bit lines provided in the same memory cell area are connected to one sense amplifier. One of the two bit lines is connected to a memory cell which reads stored content, while the other bit line is not connected to a memory cell which reads stored content. In the folded bit line system, therefore, noise generated in a target memory cell area appears in both of the paired bit lines, and thus the folded bit line system has an advantage of being resistant to noise. Meanwhile, the number of memory cells per bit line unit length of the folded bit line system is half that of the open bit line system. Therefore, the folded bit line system has a disadvantage of tending to have a larger area occupied by each memory cell.
As the structure of a capacitor included in a memory cell, a planar structure, a trench structure, a stack structure, and so forth are known. As the element isolation structure, a local-oxidation-of-silicon (LOCOS) structure, a trench isolation structure, and so forth are known. A reduction of the area occupied by each memory cell is effective to increase the integration density of memory cells. It is therefore desirable to reduce both the area occupied by the transistor and the area occupied by the capacitor.
A semiconductor device specialized for the DRAM employs a special structure called stack structure, for example, to reduce the capacitor area and increase the integration degree. Such a special structure causes no problem in the semiconductor device specialized for the DRAM. However, it is difficult to use this structure in a semiconductor device in which a memory, a logic circuit, and so forth are merged, due to a factor relating to the manufacturing process. To manufacture the merged semiconductor device in normal semiconductor processing, therefore, it is desirable to avoid a special structure such as the stack structure as the DRAM structure in the merged semiconductor device.
As an example capable of increasing the integration degree of memory cells, the following technique has been proposed. A memory cell area is divided into a plurality of sections along the bit line direction. Two upper and lower layers of bit lines are provided above the memory cells, and the memory cells are connected to the lower bit lines. The upper and lower bit lines replace each other at boundaries of the sections (i.e., in regions between adjacent sections). That is, specifically, a lower bit line replaces an upper bit line, and an upper bit line replaces a lower bit line. The bit lines are thus arranged such that one bit line serves as the lower bit line in one section and serves as the upper bit line in another adjacent section. With the two upper and lower layers of bit lines sterically intersecting with each other, the memory cells are provided at all intersections of the word lines and the bit lines even in the folded bit line system.
Further, as another example increasing the integration degree of memory cells, a technique has been proposed which provides a capacitor on a sidewall of a trench for isolating an access transistor, to thereby use the trench for providing a capacitor as well as for element isolation.
Further, as another example increasing the integration degree of memory cells, the following technique has been proposed. A local-oxidation-of-silicon (LOCOS) type field insulating layer for defining active regions is first formed, and transistors are formed in the active regions. Thereafter, a trench is formed for each of the memory cells around the active regions adjacent to the transistors, and an impurity diffusion region is formed on a surface of the trench. Then, the impurity diffusion region is covered by a dielectric film to form a counter electrode on the surface of the trench. Further, a dielectric film and a storage electrode are laminated on the region. Thereby, a capacitor is formed in which the counter electrode is sandwiched by the diffusion region and the storage electrode.
Further, as another example increasing the integration degree of memory cells, a technique has been proposed which changes the arrangement of bit lines at an intermediate position on the bit lines in the longitudinal direction thereof, to thereby reduce interference noise between the bit lines.